One time programmable (“OTP”) cells are used in integrated circuit (“IC”) devices for a variety of applications including OTP memory applications. They may be used as a single memory cell, or in arrays of memory cells to provide unique die/chip IDs and to set operating parameters such as clock multipliers and voltage levels for devices such as microprocessors. They may also be used to configure, customize, and repair a chip after testing (e.g., to repair a processor chip's cache memory array). OTP cells are typically implemented using charge storage, fuse, or antifuse approaches. Charge storage approaches have typically involved defining a bit value based on charge stored on an insulated metal oxide semiconductor (“MOS”) type gate structure. Such charge storage approaches, however, are not practicable with current and future deep sub-micron technologies that feature very thin gate oxide because of the high gate leakage current that prevents a long retention time of the information.
On the other hand, fuse and antifuse solutions are more reliable with such technologies. A fuse (or anti-fuse) link can be used to indicate a logic level (e.g., a High or Low level) depending on whether or not it is “blown” or left in its normal state. The natural state of a fuse is closed, but when it is blown (or burned), its resistance is increased to an open state (relative to its normal, closed state). In contrast, an antifuse is blown closed, with its natural state being an open circuit (relative to its normal, open state). A fuse or antifuse can thus be used to establish a logic level whose value depends upon whether it is blown or left in its normal state. Unfortunately, materials such as polysilicon and metals (used for fuses) and amorphous silicon (used for antifuses) require excessive voltages and currents (e.g., potentials exceeding 10 volts at currents greater than 10 Amps) for reliable programming. This is problematic because it means that large, robust transistor circuits are needed in each cell for reliable fuse/anti-fuse programming that does not do damage to surrounding, more sensitive circuitry. Another drawback is that the blowing of such fuse/antifuse structures is unreliable because it is not cumulative; if a device does not blow correctly the first time, it generally cannot be further blown by applying the programming current again. As a result, a certain redundancy is required to compensate for the portion of fuses/antifuses that don't blow correctly at the first try. A further drawback is that the difference of resistance between such blown and non-blown fuse/antifuse structures can be quite small (typically less than an order of magnitude), which makes it difficult to design a sensing scheme that operates reliably through process and temperature variations.
As silicon manufacturing technologies scale, the thickness of the oxide layer isolating the gate of MOS transistors scale. As a result, it has become feasible to break down this oxide by applying a sufficiently high voltage (e.g., 3 V or higher) across the oxide layer. Accordingly, oxide layers are now being used to implement antifuse elements. They are naturally open but when broken down, become closed. (For examples of oxide layers used as antifuse elements, see U.S. Pat. No. 6,686,791 to Zheng et al. and U.S. Pat. No. 6,515,344 to Wollesen.) Unfortunately, even though the required voltage to break down the gate oxide has diminished (e.g., reduced from 10 V to 3V), it still presents a danger to the fragile transistors of the circuit surrounding the oxide element being programmed. This means that the surrounding transistors should be sufficiently protected from the high programming voltages. Accordingly, disclosed herein are improved circuits for implementing antifuse cells and cell arrays using oxide (or other dielectric materials) as antifuse elements.